This invention relates to electronic devices including thin-film transistors (hereinafter termed "TFTs") on a substrate, for example a glass or insulating polymer substrate. The device may be, for example, an active-matrix liquid-crystal display or other flat panel display, or any other type of large area electronic device with TFTs in a matrix and in a drive circuit, for example, a thin-film data store or an image sensor. The invention also relates to methods of manufacturing such an electronic device.
For many years there has been much interest in developing thin-film circuits with TFTs on glass and/or on other inexpensive insulating substrates, for large area electronics applications. Such TFTs fabricated with amorphous or polycrystalline semiconductor films may form the switching elements of a cell matrix, for example, in a flat panel display as described in U.S. Pat. No. 5,130,829 (Our Ref: PHB 33646). A more recent development involves the fabrication and integration of circuits from TFTs (often using polycrystalline silicon) as, for example, integrated drive circuits for such a cell matrix. Thus, for example, published European Patent Application EP-A-0 629 003 (corresponding U.S. patent application Ser. No. 08/639277: Our Ref: PHB 33845) describes such an electronic device comprising on a substrate a switching matrix of thin-film switching transistors and a peripheral drive circuit located outside the matrix and comprising thin-film circuit transistors which are coupled to the switching TFTs of the matrix. The whole contents of U.S. Pat. No. 5,130,829 and EP-A-0 629 003 are hereby incorporated herein as reference material.
Unfortunately, undesirable field-induced effects occur in the transistor characteristics of such TFTs, especially those fabricated with polycrystalline silicon formed using low temperature processes. Several instability mechanisms occur, for example, bias-induced state creation in the polycrystalline silicon, and hot carrier induced state creation and carrier trapping. Another effect which occurs is a drain field-enhanced increase in leakage current. The degradation of the transistor characteristics (for example, off-state leakage current, threshold voltage and on-state current) can seriously limit the use of such TFTs in such circuits.
One way of reducing such effects in TFTs is by means of a field-relief region having a lower doping concentration of the one conductivity type than the drain region. The TFT comprises an insulated gate adjacent to a crystalline semiconductor film for controlling a conduction channel of one conductivity type in the semiconductor film between source and drain regions of the one conductivity type. The field relief region is present between the conduction channel and drain region of the TFT.
The article "Characteristics of Offset-Structure Polycrystalline-Silicon Thin-Film Transistors" by K. Tanaka et al. in IEEE Electron Devices Letters Vol. 9 No. 1, January 1988, describes one form of such a TFT wherein the drain region is offset from the gate by at least most of the field relief region. The resulting TFT has a reduced leakage current, as compared with a non-offset TFT structure without any field-relief region. The paper WS3/1 "Influence of Drain Field on Poly-Si TFT Behaviour" by J. R. Ayres et al. in the Proceedings of the Active Matrix Workshop (published by SID--The Society for Information Display) held with the 16th International Display Research Conference, Birmingham England, Sep. 30, 1996, discloses another form wherein at least most of the field relief region overlaps with the gate. The whole contents of this article and this paper are hereby incorporated herein as reference material.